Does x86_64 Offer True Atomic Support for Double-Precision Floating-Point Values and Vectors?

Is Assembly-Level Atomic Support Available for Doubles and Vectors in x86_64?

While C 11 std::atomic is generally lock-free on typical implementations, it faces limitations in efficiency due to potential inefficiencies in compiler-generated code. Compilers may not always produce optimal assembly for atomic operations involving floating-point values.

Additionally, C 11 std::atomic does not provide an API for Intel's transactional-memory extensions (TSX) for either integer or floating-point operations. TSX can significantly improve performance for atomic operations by eliminating overhead associated with data movement between general-purpose registers and floating-point registers.

Atomic Loads and Stores for Vectors

Despite claims that x86_64 lacks atomic support for vectors, naturally aligned loads and stores of up to 8 bytes, which includes vectors, are atomic on x86 processors. This includes loads and stores using x87 or SSE instructions. Therefore, aligned loads and stores of double-precision floating-point values are atomic.

Atomic Read-Modify-Write Operations

Atomic read-modify-write operations (such as atomic addition) are not directly supported for double-precision floating-point values or vectors. The only option for these operations on x86_64 is a retry loop using the cmpxchg instruction or TSX.

Special Cases for Atomic Operations

Some special cases for IEEE floating-point operations can be implemented using integer operations. For example, negating a double-precision floating-point value can be achieved by flipping the sign bit using an atomic operation.

Atomic Vector Loads and Stores

While there is no hardware guarantee for atomic vector loads and stores, it is generally safe to assume that aligned vector loads and stores of double-precision floating-point values will not result in tearing. However, atomic vector operations involving unaligned values may not be safe. The exception to this is with Intel's AVX feature, which guarantees 128-bit atomicity for SSE/AVX operations.

Atomic Operations on 16B Objects

To perform atomic operations on 16-byte objects, which is larger than the native atomic operation width, lock cmpxchg16b must be used. This can result in significant performance overhead compared to normal atomic operations, making it unsuitable for scenarios where performance is critical.

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